In silicon on insulator (SOI) technology a thin silicon layer is formed over an insulating layer, such as silicon oxide, which in turn is formed over a bulk substrate. This insulating layer is often referred to as a buried oxide (BOX) layer or simply as a BOX.
Electrostatic discharge (ESD) protection devices can be implemented with diodes and are widely used with CMOS devices. In partially depleted SOI (PDSOI) devices lateral diodes are conventionally used. However, direct porting of such structures into FinFET technology that may employ extremely thin SOI (ETSOI) technology can result in poor performance as the diode area is limited to the fin cross-sectional area. In fact, with typical fin heights the diode area may be only about one half to one third that of a PDSOI diode.
One possible technique to increase the diode area is to use an undoped (or n-doped) epitaxial layer (e.g., 50-70 nm in thickness) that will “thicken” the diode so that the diode is capable of delivering a current comparable to a PDSOI lateral diode. However the use of this epitaxial ‘thickening’ technique can result in significant topography variations across the chip. Furthermore the use of this technique can require a specific set of junction formation implants that would be dedicated to the diode, i.e., the implant depth for the diodes would be different from the implant depth used in the FinFET region thereby complicating the chip fabrication procedure.
Clearly there is a need to provide a lateral diode device and structure that is compatible with conventional FinFET integration techniques.